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18Mb Pipelined DDRTMII SRAM Burst of 2
Features

IDT71P71804 IDT71P71604
Description
The IDT DDRIITM Burst of two SRAMs are high-speed synchronous memories with a double-data-rate (DDR), bidirectional data port. This scheme allows maximization of the bandwidth on the data bus by passing two data items per clock cycle. The address bus operates at single data rate speeds, allowing the user to fan out addresses and ease system design while maintaining maximum performance on data transfers. The DDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. All interfaces of the DDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. Clocking The DDRII SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the DDRII has an output "echo" clock, CQ, CQ.

18Mb Density (1Mx18, 512kx36) Common Read and Write Data Port Dual Echo Clock Output 2-Word Burst on all SRAM accesses Multiplexed Address Bus One Read or One Write request per clock cycle DDR (Double Data Rate) Data Bus - Two word bursts data per clock Depth expansion through Control Logic HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V to 1.9V. Scalable output drivers Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V. Output Impedance adjustable from 35 ohms to 70 ohms 1.8V Core Voltage (VDD) 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package JTAG Interface
Functional Block Diagram
DATA REG (Note 1)
WRITE DRIVER
OUTPUT SELECT
SENSE AMPS
LD R/ W BW x
(Note3)
CTRL LOGIC
18M MEMORY ARRAY
(Note1)
OUTPUT REG
SA SA0
ADD REG
(Note2)
WRITE/READ DECODE
(Note2)
(Note4)
(Note1)
DQ
K K C C
CLK GEN SELECT OUTPUT CONTROL
6112 drw 16
CQ CQ
Notes 1) Represents 18 signal lines for x18, and 36 signal lines for x36 2) Represents 20 address signal lines for x18 and 19 address signal lines for x36. 3) Represents 2 signal lines for x18 and 4 signal lines for x36. 4) Represents 36 signal lines for x18 and 72 signal lines for x36. 1
APRIL 2006
DSC-6112/0A
(c)2006 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
The K and K clocks are the primary device input clocks. The K clock is used to clock in the control signals (LD, R/W and B Wx), the address, and the first word of the data burst during a write operation. The K clock is used to clock in the control signals (B Wx), and the second word of the data burst during a write operation. The K and K clocks are also used internally by the SRAM. In the event that the user disables the C and C clocks, the K and K clocks will also be used to clock the data out of the output register and generate the echo clocks. The C and C clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. C and C must be presented to the SRAM within the timing tolerances. The output data from the DDRII will be closely aligned to the C and C input, through the use of an internal DLL. When C is presented to the DDRII SRAM, the DLL will have already internally clocked the first data word to arrive at the device output simultaneously with the arrival of the C clock. The C and second data word of the burst will also correspond. Single Clock Mode The DDRII SRAM may be operated with a single clock pair. C and C may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the K and K clocks. DLL Operation The DLL in the output structure of the DDRII SRAM can be used to closely align the incoming clocks C and C with the output of the data, generating very tight tolerances between the two. The user may disable the DLL by holding Df low. With the DLL off, the C and C (or K and K of if C and C are not used) will directly clock the output register of the SRAM. With the DLL off, there will be a propagation delay from the time the clock enters the device until the data appears at the output. Echo Clock The echo clocks, CQ and CQ, are generated by the C and C clocks (or K, K if C, C are disabled). The rising edge of C generates the rising edge of CQ, and the falling edge of CQ. The rising edge of C generates the rising edge of CQ and the falling edge of CQ. This scheme improves the correlation of the rising and falling edges of the echo clock and will improve the duty cycle of the individual signals. The echo clock is very closely aligned with the data, guaranteeing that the echo clock will remain closely correlated with the data, within the tolerances designated. Read and Write Operations Read operations are initiated by holding Read/Write control input (R/W ) high, the load control input (LD) low and presenting the read address to the address port during the rising edge of K, which will latch the address. The data will then be read and will appear at the device output at the designated time in correspondence with the C and C clocks.
Write operations are initiated by holding the Read/Write control input (R/W ) low, the load control input (LD) low and presenting the write address to the address port during the rising edge of K, which will latch the address. On the following rising edge of K, the first word of the two word burst must be present on the data input bus DQ[x:O], along with the appropriate byte write (BWx) inputs. On the following rising edge of K, the second half of the data write burst will be accepted at the device input with the designated (BWx) inputs. DDRII devices internally store two words of the burst as a single, wide word and will retain their order in the burst. The x18 and x36 DDRll devices have the ability to address to the individual word level using the SA0 address, but the burst will continue in a linear sequence and wraps around without incrementing the SA bits. Similarly when reading x18 and x36 DDRll devices, the read burst will begin at the designated address, but if the burst is started at any other position than the first word of the burst, the burst will wrap back on itself and read the first locations before completing. The x18 and x36 DDR II devices can also use the byte write signals to prevent writing any individual bytes or word of the burst. Output Enables The DDRII SRAM automatically enables and disables the DQ[X:0] outputs. When a valid read is in progress, and data is present at the output, the output will be enabled. If no valid data is present at the output (read not active), the output will be disabled (high impedance). The echo clocks will remain valid at all times and cannot be disabled or turned off. During power-up the DQ outputs will come up in a high impedance state. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output drive impedance. The value of RQ must be 5X the value of the intended drive impedance of the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of +/- 10% is between 175 ohms and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted every 1024 clock cycles to correct for drifts in supply voltage and temperature. If the user wishes to drive the output impedance of the SRAM to it's lowest value, the ZQ pin may be tied to VDDQ.
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Definitions
Symbol Pin Function Description Data I/O signals. Data inputs are sampled on the rising edge of K and K during valid write operations. Data outputs are driven during a valid read operation. The outputs are aligned with the rising edge of both C and C during normal operation. When operating in a single clock mode (C and C tied high), the outputs are aligned with the rising edge of both K and K. When a Read operation is not initiated or LD is high (deselected) during the rising edge of K, DQ[X:O] are automatically driven to high impedance after any previous read operation in progress completes. 1M x 18 -- DQ[17:0] 512K x 36 -- DQ[35:0] Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device. 1M x 18 -- BW 0 controls DQ[8:0] and BW 1 controls DQ[17:9] 512K x 36 -- BW 0 controls DQ[8:0], BW 1 controls DQ[17:9], BW 2 controls DQ[26:18] and BW 3 controls DQ[35:27] Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations. Burst count address bit on x18 and x36 DDRll devices. This bit allows changing the burst order in read or write operations, or addressing to the individual word of a burst. See page 9 for all possible burst sequences. Load Control Logic: Sampled on the rising edge of K. If LD is low, a two word burst read or write operation will initiate as designated by the R/W input. If LD is high during the rising edge of K, operations in progress will complete, but new operations will not be initiated. Read or Write Control Logic. If LD is low during the rising edge of K, the R/ indicates whether a new operation should be a read or W write. If R/W is high, a read operation will be initiated, if R/W is low, a write operation will be initiated. If the LD input is high during the rising edge of K, the R/W input will be ignored. Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through DQ[X:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock. K is used to capture synchronous inputs being presented to the device and to drive out data through DQ[X:0] when in single clock mode. Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals are free running and do not stop when the output data is three stated. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. DQ[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
6112 tbl 02a
DQ[X:0]
Input/Output Synchronous
BW 0, BW 1, BW 2, BW 3
Input Synchronous
SA SA0
Input Synchronous Input Synchronous Input Synchronous
LD
R/ W
Input Synchronous
C
Input Clock
C K K CQ, CQ
Input Clock Input Clock Input Clock
Output Clock Input
ZQ
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Definitions continued
Symbol Pin Function Description DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet. There will be an increased propagation delay from the incidence of C and C to DQ, or K and K to DQ as configured. The propagation delay is not a tested parameter, but will be similar to the propagation delay of other SRAM devices in this speed grade. TDO pin for JTAG TCK pin for JTAG. TDI pin for JTAG. An internal resistor will pull TDI to VDD when the pin is unconnected. TMS pin for JTAG. An internal resistor will pull TMS to VDD when the pin is unconnected. No connects inside the package. Can be tied to any voltage level. Reference Voltage input. Static input used to set the reference level for HSTL inputs and outputs as well as AC measurement points. Power supply inputs to the core of the device. Should be connected to a 1.8V power supply. Ground for the device. Should be connected to ground of the system. Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage.
6112 tbl 02b
Dof f
Input
TDO TCK TDI TMS NC VREF VDD VSS VDDQ
Output Input Input Input No Connect Input Reference Power Supply Ground Power Supply
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Configuration IDT71P71804 (1M x 18)
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Dof f NC NC NC NC NC NC TDO 2 VSS/ SA (2) DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 SA NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 SA 4 R/ W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW 1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW 0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 VSS/ SA (1) NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI
6112 tbl 12b
165-ball FBGA Pinout TOP VIEW
NOTES: 1. A10 is reserved for the 36Mb expansion address. This must be tied or driven to Vss on the 1M x 18 DDRII Burst of 2 (71P71804) devices. 2. A2 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII Burst of 2 (71P71804) devices.
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Configuration IDT71P71604 (512K x 36)
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Dof f NC NC NC NC NC NC TDO 2 VSS/ SA (3) DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 NC/ SA (1) DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 SA 4 R/ W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW 2 BW 3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 BW 1 BW 0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 VSS/ SA (2) NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI
6112 tbl 12c
NOTES: 1. A3 is reserved for the 36Mb expansion address. 2. A10 is reserved for the 72Mb expansion address. 3. A2 is reserved for the 144Mb expansion address
165-ball FBGA Pinout TOP VIEW
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Write Descriptions
Signal Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 BW 0 L X X X
(1,2,3)
Linear Burst Sequence Table (1)
BW 2 X X L X BW 3 X X X L
SA0 0 1 a 0 1 b 1 0
6112 tbl 22
BW 1 X L X X
NOTE: 1. SA0 is the address presented giving the burst sequence a,b.
6112 tbl 09 NOTES: 1) All byte write (B Wx) signals are sampled on the rising edge of K and again on K. The data that is present on the data bus in the designated byte will be latched into the input if the corresponding B Wx is held low. The rising edge of K will sample the first byte of the two word burst and the rising edge of K will sample the second byte of the two word burst. 2) The availability of the B Wx on designated devices is described in the pin description table. 3) The DDRII Burst of two SRAM has data forwarding. A read request that is initiated on the cycle following a write request to the same address will produce the newly written data.
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Application Example
SRAM #1 ZQ
R=250 W
SRAM #4 ZQ SA DQ LD R/W BW 0BW 1 C C K K
R=250 W
Vt
SA LD R/W
DQ BW 0 BW 1 C C K K
R Data Bus
R
Vt R Vt
R R R
Address LD R/W BW x MEMORY CONTROLLER Return CLK Source CLK Return C LK Source C LK Vt Vt R=50W Vt =VREF
Vt
6112 drw 20
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Absolute Maximum Ratings
Symbol VTERM VTERM VTERM VTERM TBIAS TSTG IOUT Rating Supply Voltage on VDD with Respect to GND Supply Voltage on VDDQ with Respect to GND Voltage on Input terminals with respect to GND Voltage on Output and I/O terminals with respect to GND. Temperature Under Bias Storage Temperature Continuous Current into Outputs
(1) (2)
Capacitance (TA = +25C, f = 1.0MHz)(1)
Unit V V V V C C mA
6112 tbl 05
Value -0.5 to +2.9 -0.5 to VDD+0.3 -0.5 to VDD +0.3 -0.5 to VDDQ +0.3 -55 to +125 -65 to +150 + 20
Symbol CIN CCLK CO CDQ
Parameter Input Capacitance Clock Input Capacitance Output Capacitance DQ I/O Capacitance
Conditions
Max. 5
Unit pF pF pF pF
VDD = 1.8V VDDQ = 1.5V
6 7 7
6112 tbl 06 NOTE: 1. Tested at characterization and retested after any design or process change that may affect these parameters.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ must not exceed VDD during normal operation.
Recommended DC Operating and Temperature Conditions
Symbol VDD VDDQ VSS VREF TA Parameter Power Supply Voltage I/O Supply Voltage Ground Input Reference Voltage Ambient Temperature (1) Min. 1.7 1.4 0 0.68 0 Typ. 1.8 1.5 0 VDDQ/2 25 Max. 1.9 VDD 0 0.95 70 Unit V V V V
o
c
NOTE: 1. During production testing, the case temperature equals the ambient temperature.
6112 tbl 04
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8 100mV, VDDQ = 1.4V to 1.9V)
Parameter Input Leakage Current Output Leakage Current Symbol IIL IOL Test Conditions VDD = Max VIN = VSS to VDDQ Output Disabled VDD = Max, IOUT = 0mA (outputs open), Cycle Time > tKHKH Min VDD = Max, IOUT = 0mA (outputs open), Cycle Time > tKHKH Min Device Deselected (in NOP state), IOUT = 0mA (outputs open), f=Max, All Inputs <0.2V or > VDD -0.2V RQ = 250, IOH = -15mA RQ = 250, IOH = 15mA IOH = -0.1mA IOL = 0.1mA 250MHZ 200MHz 167MHz 250MHZ 200MHz 167MHz 250MHZ 200MHz 167MHz Min -2 -2 VDDQ/2-0.12 VDDQ/2-0.12 VDDQ-0.2 VSS Max +2 +2 900 800 700 850 750 650 325 300 275 VDDQ/2+0.12 VDDQ/2+0.12 VDDQ 0.2 V V V V 3,7 4,7 5 6
6112 tbl 10c
Unit A A
Note
Operating Current (x36): DDR
IDD
mA
1
Operating Current (x18): DDR
IDD
mA
1
Standby Current: NOP
ISB1
mA
2
Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage
VOH1 VOL1 VOH2 VOL2
NOTES: 1. Operating Current is measured at 100% bus utilization. 2. Standby Current is only after all pending read and write burst operations are completed. 3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175 < RQ < 350. This parameter is tested at RQ = 250 , which gives a nominal 50 output impedance. 4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175 < RQ < 350. This parameter is tested at RQ = 250 , which gives a nominal 50 output impedance. 5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an impedance measurement point. 6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance measurement point. 7. Programmable Impedance Mode.
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Input Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8 100mV, VDDQ = 1.4V to 1.9V)
PARAMETER Input High Voltage, DC Input Low Voltage, DC Input High Voltage, AC Input Low Voltage, AC SYMBOL VIH (DC) VIL (DC) VIH (AC) VIL (AC) MIN VREF +0.1 -0.3 VREF +0.2 MAX VDDQ +0.3 VREF -0.1 VREF -0.2 UNIT V V V V NOTES 1,2 1,3 4,5 4,5
6112 tbl 10d
NOTES: 1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 2. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min)) 3. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min)) 4. This conditon is for AC function test only, not for AC parameter test. 5. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC) b) Reach at leaset the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Overshoot Timing
20% tKHKH (MIN) VDD +0.5 VDD +0.25 VDD
Undershoot Timing
VIH
VSS VSS-0.25V VSS-0.5V
VIL
6112 drw 21
6112 drw 22
20% tKHKH (MIN)
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
AC Test Conditions(1)
Parameter Core Power Supply Voltage I/O Power Supply Voltage Input High Level Input Low Level Input Reference Level Input Rise/Fall Time DQ Rise/Fall Time Output Timing Reference Level Symbol VDD VDDQ VIH VIL VREF TR/TF Value 1.7 to 1.9 1.4 to VDD (VDDQ/2)+ 0.5 (VDDQ/2)- 0.5 VDDQ/2 0.3/0.3 0.5/0.5 VDDQ/2 Unit V V V V V ns V Note 2 2
NOTE: 6112 tbl 11a 1. Parameters are tested with RQ=250 2. VDDQ does not exceed VDD. During AC testing VDDQ is within 300mV of VDD.
Input Waveform
(VDDQ/2) + 0.5V VDDQ/2 (VDDQ/2) - 0.5V
6112 drw 07
Test points
VDDQ/2
Output Waveform
VDDQ/2 Test points VDDQ/2
6112 drw 08
AC Test Load
VDDQ/2 VREF OUTPUT Device Under Test ZQ Z0 =50 RQ = 250 VDDQ/2 RL = 50
6112 drw 04
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
AC Electrical Characteristics
Symbol Clock Parameters tKHKH tKC var tKHKL tKLKH tKHKH tKHKH tKHCH tKC lock tKC reset Clock Cycle Time (K,K,C,C) Clock Phase Jitter (K,K,C,C) Clock High Time (K,K,C,C) Clock LOW Time (K,K,C,C) Clock to coc (KK,CC) lk Cl to clock (KK,CC) ock Clock to data clock (KC,KC) DLL lock time (K, C) K static to DLL reset Parameter
(VDD = 1.8 100mV, VDDQ = 1.4V to 1.9V, TA =0 to 70C) (3,7)
250MHz Min. Max 200MHz Min. Max 167MHz Min. Max Unit Notes
4.00 1.60 1.60 1.80 1.80 0.00 1024 30
6.30 0.20 1.80 -
5.00 2.00 2.00 2.20 2.20 0.00 1024 30
7.88 0.20 2.30 -
6.00 2.40 2.40 2.70 2.70 0.00 1024 30
8.40 0.20 2.80 -
ns ns ns ns ns ns ns cycles ns 2 1,5 8 8 9 9
Output Parameters tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCHQZ tCHQX1 Set-Up Times tAVKH tIVKH tDVKH Hold Times tKHAX tKHIX tKHDX K,K rising edge to address hold K,K rising edge to R, W inputs hold K, K rising edge to data-in and BW x hold 0.50 0.50 0.35 0.60 0.60 0.40 0.70 0.70 0.50 ns ns ns
6112 tbl 11
C,C HIGH to output valid C,C HIGH to output hold C,C HIGH to echo clock valid C,C HIGH to echo clock hold CQ,CQ HIGH to output valid CQ,CQ HIGH to output hold C HIGH to output High-Z C HIGH to output Low-Z
-0.45 -0.45 -0.30 -0.45
0.45 0.45 0.30 0.45 -
-0.45 -0.45 -0.35 -0.45
0.45 0.45 0.35 0.45 -
-0.50 -0.50 -0.40 -0.50
0.50 0.50 0.40 0.50 -
ns ns ns ns ns ns ns ns
3 3 3 3
3,4,5 3,4,5
Address valid to K,K rising edge R, W inputs valid to K,K rising edge Data-in and BW x valid to K, K rising edge
0.50 0.50 0.35
-
0.60 0.60 0.40
-
0.70 0.70 0.50
-
ns ns ns
6
6
NOTES: 1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable. 3. If C,C are tied High, K,K become the references for C,C timing parameters. 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions (0C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. 5. This parameter is guaranteed by device characterization, but not production tested. 6. All address inputs must meet the specified setup and hold times for all latching clock edges. 7. During production testing, the case temperature equals TA. 8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH). 9. Clock to cok time (tKHKH) and C o k to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH). lc lc
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Timing Waveform of Combined Read and Write Cycles
NOP 1 Read A0 (burst of 2) 2 Read A1 (burst of 2) 3 NOP 4 NOP (Note 1) 5 Write A2 (burst of 2) 6 Write A3 Read A4 (burst of 2) (burst of 2) 8 7 9 10
K
tKHKL tKLKH tKHKH tKHKH
K
(NOTE 2)
LD
tIVKH tKHIX (NOTE 1)
R/W
SA
A0
A1
A2
A3
A4
tAVKH tKHAX tKHDX tDVKH tKHDX tDVKH
DQ
Qx1
tKHCH
Q00
Q01
Q10
Q11
D20
D21
D30
D31
Q40
Q41
tCHQV tKHCH tCHQV tCHQX tCHQX1
tCHQZ tCHQX
tCQHQV
tCQHQX
C
tKHKL tKLKH tKHKH tKHKH
C
tCHCQV tCHCQX
CQ
tCHCQV tCHCQX
CQ
6112 drw09
NOTE:
1. If a R/W is low on the next rising edge of K after a read request, the device automatically performs a NOP (No Operation.) 2. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent the bus contention.
6.42 14
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up; therefore, the TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 0 0 0 0 IR1 0 0 1 1 0 0 1 1 IR0 0 1 0 1 0 1 0 1 Instruction EXTEST IDCODE SAMPLE-Z RESERVED TDO Output Boundary Scan Register Identification register Boundary Scan Register Do Not Use 2 1 5 4 5 5 3 Notes
SRAM CORE
1 1 1
SAMPLE/PRELOAD Boundary Scan register RESERVED RESERVED BYPASS Do Not Use Do Not Use Bypass Register
TDI
BYPASS Reg. Identification Reg. Instruction Reg. Control Signals
TDO
1
TMS TCK
TAP Controller
6112 drw 18
6112 tbl 13 NOTE: 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initialized to Vss when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 4. SAMPLE instruction does not place output pins in Hi-Z. 5. This instruction is reserved for future use.
TAP Controller State Diagram
1 Test Logic Reset 0 Run Test Idle 0 1 1 Select DR 0 Capture DR 0 Shift DR 1 1 Exit 1 DR 0 Pause DR 1 Exit 2 DR 1 1 Update DR 0 1 1 1 Select IR 0 Capture IR 0 Shift IR 1 Exit 1 IR 0 Pause IR 0 0 1 Exit 2 IR 1 Update IR 1 0 0 0 1
0
0
6112 drw 17
6.42 15
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Scan Register Definition
Part 512K x36 1Mx18 Instrustion Register 3 bits 3 bits Bypass Register 1 bit 1 bit ID Register 32 bits 32 bits Boundary Scan 107 bits 107 bits
6112 tbl 14
Identification Register Definitions
INSTRUCTION FIELD Revision Number (31:29) Device ID (28:12) IDT JEDEC ID CODE (11:1) ID Register Presence Indicator (0) ALL DEVICES 0x0 0x0294 0x0295 0x033 1 DESCRIPTION Revision Number 512Kx36 1Mx18 DDRII BURST OF 2 71P71604S 71P71804S PART NUMBER
Allows unique identification of SRAM vendor. Indicates the presence of an ID register.
6112 tbl 15
6.42 16
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Boundary Scan Exit Order (1M x 18-Bit)
ORDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PIN ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E
6112 tbl 16
ORDER 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN ID 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 1H 1A 2B 3B 1C 1B 3D 3C 1D
6112 tbl 17
ORDER 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107
PIN ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R
6112 tbl 18
6.42 17
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Boundary Scan Exit Order (512K x 36-Bit)
ORDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PIN ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 9P 10N 10P 11M 9N 9M 11N 11L 10L 9L 10M 11K 9K 9J 10K 11J 9G 11H 10G 10J 11F 10F 9F 11G 11E 9E
6112 tbl 16b
ORDER 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN ID 10D 10E 11C 9D 9C 11D 11B 10B 9B 10C 11A Internal 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 1H 1A 3B 1B 1C 2B 3D 2C 1D
6112 tbl 17b
ORDER 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107
PIN ID 3C 3E 1E 2E 2D 3F 1F 1G 2F 3G 2J 1J 2G 3K 1K 2K 3J 3L 1L 1M 2L 3N 2M 1N 3M 3P 1P 2P 2N 3R 4R 4P 5P 5N 5R
6112 tbl 18b
6.42 18
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
JTAG DC Operating Conditions
Parameter I/O Power Supply Power Supply Voltage Input High Level Input Low Level TCK Input Leakage Current TMS, TDI Input Leakage Current TDO Output Leakage Current Output High Voltage (IOH = -1mA) Output Low Voltage (IOL = 1mA) Symbol VDDQ VDD VIH VIL IIL IIL IOL VOH VOL Min 1.4 1.7 1.3 -0.3 -5 -15 -5 VDDQ - 0.2 VSS Typ 1.8 Max VDD 1.9 VDD+0.3 0.5 +5 +15 +5 VDDQ 0.2 Unit V V V V A A A V V 1 1 Note
6112 tbl 19 NOTE: 1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to ZQ.
JTAG AC Test Conditions
Parameter Input High Level Input Low Level Input Rise/Fall Time Input and Output Timing Reference Level Symbol VIH VIL TR/TF Min 1.8 0 1.0/1.0 0.9 Unit V V ns V 1
6112 tbl 20
Note
NOTE: 1. For SRAM outputs see AC test load on page 12.
JTAG Input Test Waveform
1.8 V 0.9 V 0V
6112 drw 23
JTAG AC Test Load
0.9 V
Test points
0.9 V
50 Z0 = 50 TDO
6112 drw 25
JTAG Output Test Waveform
0.9 V Test points 0.9 V
6112 drw 24
,
6.42 19
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
JTAG AC Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLQV Min 50 20 20 5 5 5 5 5 5 0 Max 10 Unit ns ns ns ns ns ns ns ns ns ns
6112 tbl.21
Note
JTAG Timing Diagram
TCK
tCH C H tM V C H
TMS T D I/ SRAM Inpu ts SRAM O utputs TDO
tD V C H
tCH C L tCH M X
tC L C H
tCH D X
tSVC H
tC H S X
tCLQ V
6112drw 19
6.42 20
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
6.42 21
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Ordering Information
IDT 71P71XXX Device Type S Power XXX Speed BQ Package
BQ
165 Fine Pitch Ball Grid Array (fBGA)
250 200 167
Clock Frequency in MegaHertz
IDT71P71804 1M x 18 DDR II SRAM Burst of 2 IDT71P71604 512K x 36 DDR II SRAM Burst of 2
6112 drw 15
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com
for Tech Support: sramhelp@idt.com 408-284-4532
"QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. "
6.42 22
IDT71P71804 (1M x 18 x -Bit) 71P71604 (512K x 36-Bit) 18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Revision History
REVISION 0 A DATE 07/29/05 04/21/06 PAGES 1-24 1-3,7,8,10,13, 16,17,22 9,12,19 10 12 DESCRIPTION Released Final datasheet Removed 2Mx8 (71P71204) and 2Mx9 (71P71104) device options. Clarified VDDQ maximum value equals VDD. Updated IDD operating current for x36 and x18 options. Added clarification for VDDQ and VDD values for AC test condition.

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